data processor的例句大全

In this paper, the data path of a high performance reconfigurable DSP processor is introduced.

介绍了高性能定点可重构DSP处理器的数据通路设计.

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But from the simulation data we can find out consumption optimization complies with Amdahl law too. Only optimizing a part is not enough, no matter cache but also issue queue, the optimization proportion of the total consumption of the processor is under 10% basically.

但是从模拟数据也可以看出，功耗优化一样遵从Amdahl定律，仅仅优化一个部件的功耗是不够的，无论动态低功耗自适应Cache还是发射队列，处理器总功耗的优化比例基本在10%以下。

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Signal Conditioner With Data Converter and Processor Function

具有数据转换和处理功能的信号调理器

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Compile the complete computer processor, from data analysis, data pretreatments and the complete computer processor was all compiled to linear a series of courses laying down to the trouble simulation checkout building pattern and checkout tactics, and makes the application of this method become simply workably;

编写了完整的计算机处理程序，从数据分析、数据预处理、线性建模、检测策略的制定到故障仿真检测的一系列过程都编写了完整的计算机处理程序，使这一方法的运用变得简单可行；

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The data processor is the user graphical interface procedure, slights the law the new sales cycle starts, as well as the data compiles, opens the prize, sends the color and so on all work all to complete in this procedure.

数据处理器是用户图形界面程序，玩法的新销售周期开始，以及数据汇总，开奖，派彩等的所有工作都在该程序中完成。

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A generalized processor sharing type optimization is used to implement a channel-aware parallel WFQ for the scheme. The algorithm can optimize total throughput while guaranteeing the minimum data rate requirement for multimedia users.

在资源分配上，基于广义处理机共享（GPS）优化模型提出基于信道状态的并行加权公平队列（Cap-WFQ）调度和功率分配算法，算法在保证多媒体用户的最小数据率要求的同时优化系统的吞吐量。

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The purpose of the article is designing and carrying out the QDR using FPGA which is a high speed and easy modifying. The QDR links the processor and interface which are both in the high speed data communication system.

旨在通过FPGA的快速、灵活、容易修改的特点，设计并实现在高速数据通信系统中，QDR静态存储器用于处理器和接口连接的外设之间的数据交换。

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Data processing module with a close-coupled master-slave dual processors employs a digital signal processor ( DSP) as its data processor and a micro-controller as its I/ O interface processor.

数据处理模块采用主从式紧耦合双处理器结构，分别以数字信号处理器（DSP）作为数据处理机，单片微控制器作为I/O接口处理机；

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Signal integrity design for the pivotal circuit of high speed signal processor is achieved by the scheme, in which, including signal ordination module, high-speed AD module, data processing module, EMC module and power integrity module.

利用此方案，对高速信号处理机关键电路进行了信号完整性设计，包括信号调理模块、高速AD模块、数据处理模块、电磁兼容性模块和电源完整性模块等。

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The architecture of a reconfigurable data path DSP with low power, high speed and good flexibility as the center processor of personal information assistant ( PIA) SoC is investigated.

研究了一种基于可重构数据路径的信号处理器结构。其具有功耗低，速度快，灵活性较高等特点，可以做为个人信息处理SoC的核心处理器。

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It adopts high-performance DSP ( TMS320C6203) as the core chip to design the high speed processor and system controller to make them effectively fulfill high data volume and high speed image control and guide information processing.

采用高性能DSP（TMS320C6203）为核心，设计了高速处理器和系统控制器，使得高速处理器和系统控制器能够高效地完成大数据量、高速度的图像制导信息处理。

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This paper describes a microprogrammed emulator for a large MIMD ( multiple instruction stream-multiple data stream) parallel processor system. This emulator is intended for use in the testing performances of the target parallel processor system and debugging its application code prior to its actual implementation.

本文叙述一个大型MIMD（多指令流多数据流）并行处理系统的微程序仿真器，该仿真器可在目标系统实现之前调试要运行的应用程序及量测目标系统的性能。

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Based on the skew cyclic convolution distributed algorithm presented by W. Li [ 1], a 2-dimensional 8 × 8 DCT/ IDCT real-time processor utilizing FPGA has been designed, which can be used for high data rate applications.

在W.Li提出的循环斜卷积分布算法〔1〕的基础上，利用FPGA设计可用于高速数据传输设备的二维8×8DCT／IDCT实时处理器。

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In the interactive mode, the commands allow the processor to read/ modify memory areas, set environment variables, download data from the serial port or from the Ethernet interface and execute code routines.

在其交互模式下使用有关命令可以进行对存储区进行读取和修改、设置环境变量、通过串口或以太网接口下载并执行常规代码等操作。

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Microcontroller Integrated Circuit with Read Only Memory Microcontroller integrated circuit comprises a processor core which exchanges data with at least one data processing and storage device.

单片机集成电路包含一个处理器内核，它至少通过一种数据处理或存储设备来交换数据。

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The data ready line can be used to flag the processor when a keystroke is ready to be read.

当按下的键准备读出时，数据准备线可用来作处理器的标志。

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Functional Test and Fault Test Data Compression on Digital Signal Processor IP Core

数字信号处理器IP核功能测试及故障测试数据压缩方法

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The dar ( Data Address Register) contains the address that the processor tried to access, which then caused a page fault.

dar（数据地址寄存器）包含处理器尝试访问的地址，这一行为将引发页面错误。

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HDLC is a high level data link control protocol. It's function can be realized by special HDLC processor or FPGA.

HDLC（高级数据链路控制）协议的功能可由专用的HDLC处理芯片或FPGA（现场可编程门阵列）实现。

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Funds were raised, mainly by parents, that enabled the school to gain access to a computer-a Program Data processor ( PDP)-through a teletype machine.

学校主要靠家长提供的资金通过一种电传打字机进入电脑——即程序数据处理机。

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