interrupt controller的例句大全

The software of the controller incudes main programme and the realtime interrupt program.

软件部分包括主程序和实时中断程序.

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VxWorks realtime systems in the interrupt controller driver source code.

VxWorks实时系统中的中断控制器驱动程序源代码.

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In this paper, the architecture of the Advanced Programmable Interrupt Controller ( APIC) System is introduced, and the Local APIC module, I/ O APIC module and APIC BUS are discussed in detail.

本文介绍了高级可编程中断控制器（APIC）系统的构成，并对其中的Local APIC模块、I/O APIC模块以及A-PIC总线作了详细的介绍。

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Reduction of interrupt controller IP applying in 32 bits embedded system

应用于32位嵌入式系统的中断控制IP的裁减设计

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The research and design of interrupt controller in DSP

DSP中断控制器的实现

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Research on a kind of interrupt controller IP core applying in embedded system

一种应用于嵌入式系统中断控制IP核的研究

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IP Design of Interrupt Controller Based on CPLD

基于CPLD的中断控制器IP设计

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Research on Advanced Programmable Interrupt Controller Systems

高级可编程中断控制器系统的研究

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Microcomputer Interrupt Controller Work Type Analyze

微机中断控制器工作方式简析

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The interrupt controller hardware sends interrupts to any CPU.

中断控制器硬件可以将中断发送到任何CPU。

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This paper analyzes the whole functions and separate modules of memory controller and interrupt controller and introduces the normal IP design flow.

本文详细分析了内存控制器和中断控制器的总体功能以及内部各个模块的划分，介绍了一般IP设计流程。

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Although different SoC platform will have different modules, there are some necessary modules, such as memory controller and interrupt controller.

不同的SoC平台中，可能包含的模块各不相同。但是内存控制器和中断控制器是必不可少的。

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The interrupt controller hardware needs to recognize the source of the interrupt and which partition should receive that interrupt.

中断控制器硬件需要确定中断源，以及应该接收该中断的分区。

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Supplemental facilities include debug unit for real-time debugging, high resolution tick timer, programmable interrupt controller and power management support.

辅助功能包括用于实时调试的调试单元，高分辨率嘀哒计数器，可编程中断控制器和电源管理。

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Especially the development of the multi-core processors leads to the increasingly complex communication, and the interrupt controller plays an important role in communication of Microprocessor.

尤其是随着处理器向多核迈进，核与核之间的握手通信越来越复杂，中断控制器担当的任务也越来越重要。

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As mentioned before, the mapping between IRQs and vectors can be modified by issuing suitable I/ O instructions to the Interrupt Controller ports.

IRQ与向量之间的映射可以通过发出合适的I/O指令给中断控制器端口来修改。

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The default system configuration includes a bunch of peripherals: an interrupt controller, 16550-compatible UART, a dual PS/ 2 device controller to handle the mouse and keyboard ports, and much more.

默认系统配置包括一组外围设备：一个中断控制器、一个16550兼容的UART、一个双PS/2设备控制器（处理鼠标和键盘端口），等等。

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It is mainly composed of DMA controller ( 82C37), interrupt controller ( 82C59), programmable interval timers ( 82C54), DRAM refresh control, wait state generator and system reset logic.

其内部主要由DMA控制器（82C37）、中断控制器（82C59）、可编程间隔计时器（82C54），DRAM刷新控制器，等待状态产生器，系统重置电路组成。

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Interrupt controller is its sub-module, which performance directly affect the effectiveness of program and the whole performance of DSP. This paper takes 32 bits generic DSP as an example, explain the hardware optimization and realization of interrupt controller.

而中断控制器作为此模块中的子模块，其性能的优劣直接影响到程序的效率和DSP的整体性能，本文以32位通用DSP为例，详细阐述中断控制器的硬件优化与实现。

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