timing sampling的例句大全

For data collecting, use FPGA to conform the sampling data according the timing of ADC.

数据采集模块，根据ADC输出时序用FPGA对采样数据进行整合，以供后级处理。

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Secondly, the effects of carrier frequency offset, sampling clock offset, and symbol timing offset on OFDM signals are exploited.

其次本文分析了符号定时误差、采样时钟偏差、频率偏差对解调信号的影响。针对符号定时同步问题，阐述了利用OFDM帧头训练序列同步的方法；

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This thesis analyzes some influences on the performances of OFDM digital communications, which include carrier frequency offset, symbol timing offset and sampling clock offset.

分析了载波频率偏差、符号定时偏差和样值频率偏差对OFDM系统性能的影响。

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Secondly, the basic theory of OFDM system and the system model are introduced, and the errors of timing synchronization, frequency synchronization and the sampling rate synchronization are discussed in detail.

其次介绍了OFDM技术的基本原理，给出了OFDM信号的特性以及一般OFDM系统的构成模型，仔细分析了三种同步误差（定时偏差、载波频率偏差、采样时钟频偏）对OFDM解调性能的影响。

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Reversal current chronopotentiometry have to restrict sampling interval. To solve this problem, timing control is applied in electric relay. Timer control which is included in Delphi is used in the program. Program of controlling electric relay is executed every 4 seconds.

为了解决使用电流反向法必须要限制采样间隔的问题，我们对继电器实施定时控制，在编程中使用Delphi中的时钟控件（timer），每4秒钟执行一次程序。

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Interpolation theory in digital signal processing has application in timing synchronization, which makes the sampling clock independent of the timing control so that timing adjustment is realized completely through digital disposal. The issue of interpolation in timing synchronization is discussed.

论文探讨了数字信号处理中插值理论在定时同步中的应用，它使得接收端的采样时钟独立于定时控制，定时调整完全通过数字处理方法得以实现。

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Application of the technology of sampling in different phase in clock circuit realizes maximum 200M equivalent sampling rate of timing analyzer.

在时钟电路中采用分相采样技术，实现了定时分析最高200M的等效采样速率。

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Following the introduction of the basic principle of OFDM, some nonideal effects on the performance of OFDM systems are discussed, such as carrier frequency offset, symbol timing offset and sampling clock deviation.

本文在简要介绍了OFDM的基本原理、关键技术的基础上，针对同步问题进行了深入研究。首先分析了同步偏差中的频率偏差、符号定时偏差及采样时钟偏差对系统性能的影响。

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This board uses two chips, six channels A/ D converter and phase locking synchronous technology for collecting three-phase voltage and current signals in timing and equal-time cycle sampling ways, and the gained data make more reasonable for power quality norm analysis.

并采用了两片六通道高速A/D转换器和运用了锁相同步技术，对三相电压和电流信号能进行定时采样和等间隔采样，这样得到的数据对于下一步电能质量指标进行分析更为合理。

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Research of timing information extractions and digital line-locked sampling of video signal in free-running sampling system

自由采样下视频信号的时序提取与数字行锁相的研究

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The influence of timing jitter and amplitude fluctuation of the sampling pulses is also investigated.

同时我们还研究了采样光脉冲时间抖动和幅度抖动对光性能监测系统的影响。

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To achieve fine symbol timing, a loop controlled by numerical controlled oscillator ( NCO) was used to track the residual timing error and the sampling frequency error after coarse timing acquisition based on a preamble.

基于前导字进行粗同步估计，并采用数字控制振荡器（NCO）控制的环路对残留符号定时误差和采样频率偏差进行跟踪补偿，以获得精确符号同步。

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This timer ′ s programmable count range is 16 bits, timing precision is 8 ps, and equivalent sampling rate is up to 50 GHz.

可编程计数范围为16bit，实际最小定时单位达8ps，折合采样频率高达50GHz。

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But, to the development prospect of the PRML, the sampling frequency becomes higher, so that the request of the timing precision also becomes higher. So, the research of the high-performance timing recovery technology is urgently needed.

PRML通道不断发展的过程中，所需采样率在不断提高，而准确译码对判决定时精度的要求也随之增高，所以，研究高性能的时钟恢复技术也成为硬盘读写通道研究的迫切需要。

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A new type read out circuit is composed with one dynamic source follower, one capacitance for sampling and holding and one reset switch. This circuit has advantages with simple structure, acquiring related timing easily, single output, and so on.

采用一种新型结构的读出电路，该电路包含一个动态源随器和一个采样保持电容和一个复位开关，结构简单，时序容易实现，并且是单端输出，有着诸多优点。

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The real time measuring system of high speed rotating blade vibration, tip timing sensor, pulse signal sampling system and analysis processing of blade vibration signal are researched.

研究了高速旋转叶片振动实时监测系统，叶端定时传感器、传感器脉冲信号采集电路和叶片振动信号的实时分析和处理。

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